Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming (sometimes referred to as writing) of charge storage nodes, such as floating gates, trapping layers, or other physical phenomena, determine the data value of each cell. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, cellular telephones, and removable memory modules.
A NAND flash memory device is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash memory devices is arranged such that the control gate of each memory cell of a row of the array is connected together to form an access line, such as a word line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series, source to drain, between a pair of select lines, a source select line and a drain select line. A “column” refers to a group of memory cells that are commonly coupled to a local data line, such as a local bit line. It does not require any particular orientation or linear relationship, but instead refers to the logical relationship between memory cell and data line.
The source select line includes a source select gate at each intersection between a NAND string and the source select line, and the drain select line includes a drain select gate at each intersection between a NAND string and the drain select line. The select gates are typically field-effect transistors. Each source select gate is connected to a source line, while each drain select gate is connected to a data line, such as column bit line.
The charge storage node for memory cells of some NAND flash memory devices is a conductor, e.g., a floating gate. A dielectric (e.g., sometimes termed an interlayer dielectric) is formed over the floating gate and a control gate is formed over the dielectric. The conductor forming the floating gate is typically of polysilicon. The control gate may also include polysilicon disposed on the interlayer dielectric layer and a conductor, such as metal or metal silicide, disposed on the polysilicon.
Sometimes select gates are formed concurrently with memory cells and thus have the same layers in their gate stacks as the memory cells. For example, a select gate may include a first conductor, corresponding to the floating gates of the memory cells, e.g., of polysilicon, a dielectric, corresponding to the interlayer dielectric of the memory cells, over the first conductor, and a second conductor, corresponding to control gate of the memory cells, e.g., having polysilicon over the dielectric and metal or metal silicide over the polysilicon. However, it is desirable that the select gates and the memory cells operate differently. That is, it is desirable to eliminate the effect of the dielectric between the first and second conductors.
Shorting the polysilicon of the first conductor and the polysilicon of the second conductor together to form a control gate of the select gate is one way to eliminate the effect of the dielectric from a select gate. The first and second conductors may be of different doping types. This will create a p-n junction when the contact is made through the dielectric which acts to increase the select gate resistance.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative select gates and the methods for their formation.